1. Field of the Invention
The present invention relates to a bridge-less boost (BLB) power factor correction topology, and more particularly to such a circuit controlled with one cycle control and/or comprising bidirectional switches.
2. Description of the Related Art
Power factor correction is required by international standards (EN61000-3-2) to reduce harmonic emissions in AC powered systems.
The most common solution, shown in FIG. 1, uses typically an input rectifier bridge, made of four diodes of appropriate voltage rating followed by a boost switching converter, controlled by a voltage loop and a current loop. The outer voltage loop via diode DV will tend to maintain the output voltage approximately constant. The inner current loop via diode DL (indicated by arrows) will shape the input current to track the instantaneous input voltage.
Typically the input voltage is sensed by the controller PFC PWM to generate a reference signal for the current. The current is also sensed by the control circuit. Thus the input voltage and current will be proportional at all times, generating the desired resistive behavior at the input of the system.
This known circuit has several disadvantages. The path of the current goes through three diodes in series (two in the input bridge plus the output boost diode DL) causing high conduction losses especially at high current levels. The inrush current control (NTC device and relay) also affects performance. The PFC PWM controller usually must sense the rectified input line voltage, as well as the output voltage and the instantaneous inductor current, in order to be able to achieve both power factor correction and load regulation. Moreover, this circuit has redundant rectification, by the input bridge on the one hand, and by the boost inductor L on the other.
FIG. 7 shows a prior art PFC topology as disclosed in U.S. Pat. No. 4,412,277, incorporated by reference, which uses a traditional control technique using an analog multiplier. This topology is undesirable at least because the controlled switches cannot be driven at the same time, but need to have separate gate drives, properly out of phase.
FIG. 8 shows another prior single phase dual boost topology. A disadvantage of this circuit is the reverse recovery of the high side switch, which would make the implementation impractical. This problem is overcome in the present bridgeless solution wherein a hyperfast boost diode may be used. The prior method is a “passive PFC” and requires a resonant or snubbing network to achieve results. The present bridgeless PFC is an active method and can utilize either hard or soft switching.
Also of interest are U.S. Pat. No. 5,335,163; U.S. Pat. No. 4,899,271; EP 1 198 058 A1; and High Efficient PFC-stage without Input Rectification, Prof. Dr. Manfred Reddig and Dr. Manfred Schlenk, PCIM Conference Proceeding 2003; all of whose disclosures are incorporated by reference.